The present invention relates to a circuit arrangement for processing sampled analog electrical signals, each sample being in the form of a current, the circuit arrangement comprising means for combining in predetermined proportions the input sample current in a present sample period with current(s) derived from input sample current(s) in one or more preceding sample periods, and means for deriving the processed output signal as or from the combined current produced by the combining means in successive sample periods.
Such a circuit arrangement is disclosed in EP-A-308008, which corresponds to U.S. Pat. No. 4,864,217 (Sep. 5, 1989), and a class of such circuits has been referred to as switched current circuits. Switched current circuits can be used in place of conventional switched capacitor circuits for analog signal processing. Current mirror and/or current conveyor circuits may be used as current scaling circuits in such circuit arrangements and may implement coefficients used in the algorithms used to define circuit functions by producing the appropriate current ratios. Where these ratios are integers they can be reliably and relatively accurately achieved by using multiples of unit transistors. In general, however, the coefficients and hence the current ratios will not be integers. Clearly, the dimensions of transistors, for example, the channel width/length ratios of MOS transistors, used to implement the current mirror or current conveyor circuits could be chosen to have the desired non-integer ratios. However, if this solution is adopted there are a number of `edge-effects` which cause errors in the active or effective channel width and consequently cause an error in defining the coefficients. Examples of such edge-effects include incorrect mask dimensions or incorrectly etched windows. The effects of these errors may be reduced by using larger transistors but this is wasteful of chip area.
Current conveyor circuits are circuits in which current is conveyed between two ports at greatly different impedance levels. The current conveyor is a three port network with three ports which can be denoted x, y, and z. Its terminal characteristics can be represented by a hybrid matrix giving the outputs of the three ports in terms of their corresponding inputs. For a first generation current conveyor (CCI), this relationship is: ##EQU1##
For a second generation current conveyor (CC2) this relationship is: ##EQU2##
Further information concerning current conveyors and their implementation can be obtained by reference to the paper entitled "Current Conveyors: A Review of the State of Art" by Umesh Kumar, published in IEEE Circuits and Systems Magazine Vol. 3, No. 1, 1981, pages 10 to 14 and in the references cited therein. As discussed in that publication, the transfer characteristic between ports x and z is that of a current controlled current source with a virtual short circuit at input x. The output impedance at port z can be made very high by techniques such as cascoding, thus giving a large difference between input and output impedances. The very low (virtual short circuit) input impedance allows a more accurate current summing when the input to the current conveyor forms the summing node.